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tm 74ac573, 74act573 octal latch with 3-state outputs march 2007 ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 74ac573, 74act573 octal latch with 3-state outputs features i cc and i oz reduced by 50% inputs and outputs on opposite sides of package allowing easy interface with microprocessors useful as input or output port for microprocessors functionally identical to 74ac373 and 74act373 3-state outputs for bus interfacing outputs source/sink 24ma 74act573 has ttl-compatible inputs general description the 74ac573 and 74act573 are high-speed octal latches with buffered common latch enable (le) and buffered common output enable (oe ) inputs. the 74ac573 and 74act573 are functionally identical to the 74ac373 and 74act373 but with inputs and out- puts on opposite sides. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. pb-free package per jedec j-std-020b. note: 1. device available in tape and reel only. order number package number package description 74ac573sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74ac573sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74ac573mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act573sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74act573scx_nl (1) m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74act573sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74act573mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act573pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide fact is a trademark of fairchild semiconductor corporation .
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 2 logic symbols connection diagram pin descriptions truth table h = high voltage l = low voltage z = high impedance x = immaterial o 0 = previous o 0 before high-to-low transition of latch enable functional description the 74ac573 and 74act573 contain eight d-type latches with 3-state output buffers. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d-type input changes. when le is low the latches store the information that was present on the d-type inputs a setup time preceding the high-to-low transition of le. the 3-state buffers are controlled by the output enable (oe ) input. when oe is low, the buffers are enabled. when oe is high the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. ieee/iec pin names description d 0 ? 7 data inputs le latch enable input oe 3-state output enable input o 0 ? 7 3-state latch outputs inputs outputs oe le d o n lhh h lhl l llx o 0 hxx z
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 3 logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 4 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ?.5v to +7.0v i ik dc input diode current v i = ?.5v v i = v cc + 0.5v ?0ma +20ma v i dc input voltage ?.5v to v cc + 0.5v i ok dc output diode current v o = ?.5v v o = v cc + 0.5v ?0ma +20ma v o dc output voltage ?.5v to v cc + 0.5v i o dc output source or sink current ?0ma i cc or i gnd dc v cc or ground current per output pin ?0ma t stg storage temperature ?5? to +150? t j j unction temperature 140? symbol parameter rating v cc supply voltage ac act 2.0v to 6.0v 4.5v to 5.5v v i input voltage 0v to v cc v o output voltage 0v to v cc t a operating temperature ?0? to +85? ? v / ? t minimum input edge rate, ac devices: v in from 30% to 70% of v cc , v cc @ 3.0v, 4.5v, 5.5v 125mv/ns ? v / ? t minimum input edge rate, act devices: v in from 0.8v to 2.0v, v cc @ 4.5v, 5.5v 125mv/ns
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 5 dc electrical characteristics for ac notes: 2. all outputs loaded; thresholds on input associated with output under test. 3. i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . 4. maximum test duration 2.0ms, one output loaded at a time. symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units t yp. guaranteed limits v ih minimum high level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 2.1 2.1 v 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 0.9 0.9 v 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 i out = ?0? 2.99 2.9 2.9 v 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 v in = v il or v ih :v 3.0 i oh = ?2ma 2.56 2.46 4.5 i oh = ?4ma 3.86 3.76 5.5 i oh = ?4ma (2) 4.86 4.76 v ol maximum low level output voltage 3.0 i out = 50? 0.002 0.1 0.1 v 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 v in = v il or v ih : 3.0 i ol = 12ma 0.36 0.44 4.5 i ol = 24ma 0.36 0.44 5.5 i ol = 24ma (2) 0.36 0.44 i in (3) maximum input leakage current 5.5 v i = v cc , gnd ?.1 ?.0 ? i old minimum dynamic output current (4) 5.5 v old = 1.65v max. 75 ma i ohd 5.5 v ohd = 3.85v min. ?5 ma i cc (3) maximum quiescent supply current 5.5 v in = v cc or gnd 4.0 40.0 ? i oz maximum 3-state leakage current 5.5 v i (oe) = v il , v ih ; v i = v cc , gnd; v o = v cc , gnd ?.25 ?.5 ?
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 6 dc electrical characteristics for act notes: 5. all outputs loaded; thresholds on input associated with output under test. 6. maximum test duration 2.0ms, one output loaded at a time. symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units t yp. guaranteed limits v ih minimum high level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 2.0 2.0 v 5.5 1.5 2.0 2.0 v il maximum low level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 0.8 0.8 v 5.5 1.5 0.8 v oh minimum high level output voltage 4.5 i out = ?0 ? 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v in = v il or v ih : 4.5 i oh = ?4ma 3.86 3.76 5.5 i oh = ?4ma (5) 4.86 4.76 v ol maximum low level output voltage 4.5 i out = 50 ? 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v in = v il or v ih : 4.5 i ol = 24ma 0.36 0.44 5.5 i ol = 24ma (5) 0.36 0.44 i in maximum input leakage current 5.5 v i = v cc , gnd ?.1 ?.0 ? i oz maximum 3-state leakage current 5.5 v i = v il , v ih ; v o = v cc , gnd ?.25 ?.5 ? i cct maximum i cc /input 5.5 v i = v cc ?2.1v 0.6 1.5 ma i old minimum dynamic output current (6) 5.5 v old = 1.65v max. 75 ma i ohd 5.5 v ohd = 3.85v min. ?5 ma i cc maximum quiescent supply current 5.5 v in = v cc or gnd 4.0 40.0 ?
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 7 ac electrical characteristics for ac note: 7. voltage range 5.0 is 5.0v ?0.5v. voltage range 3.3 is 3.3v ?0.3v. ac operating requirements for ac note: 8. voltage range 5.0 is 5.0v ?0.5v. voltage range 3.3 is 3.3v ?0.3v. symbol parameter v cc (v) (7) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units min. typ. max. min. max. t phl propagation delay, d n to o n 3.3 0.5 8.5 10.5 2.5 11.0 ns t plh 5.0 1.5 5.5 7.0 1.5 7.5 t plh propagation delay, le to o n 3.3 2.5 8.5 12.0 2.5 12.5 ns t phl 5.0 2.0 6.0 8.0 2.0 8.5 t pzl output enable time 3.3 2.5 8.5 13.0 2.5 13.5 ns t pzh 5.0 1.5 6.0 8.5 1.5 9.0 t phz output disable time 3.3 1.0 9.0 14.5 1.0 15.0 ns t plz 5.0 1.0 6.0 9.5 1.0 10.0 symbol parameter v cc (v) (8) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units t yp. guaranteed minimum t s setup time, high or low, d n to le 3.3 0 3.0 3.0 ns 5.0 0 3.0 3.0 t h hold time, high or low, d n to le 3.3 0 1.5 1.5 ns 5.0 0 1.5 1.5 t w le pulse width, high 3.3 2.0 4.0 4.0 ns 5.0 2.0 4.0 4.0
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 8 ac electrical characteristics for act note: 9. voltage range 5.0 is 5.0v ?0.5v. ac operating requirements for act note: 10. voltage range 5.0 is 5.0v ?0.5v. capacitance symbol parameter v cc (v) (9) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units min. typ. max. min. max. t plh propagation delay, d n to o n 5.0 2.5 6.0 10.5 2.0 12.0 ns t phl t plh propagation delay, le to o n 5.0 3.0 6.0 10.5 2.5 12.0 ns t phl propagation delay, le to o n 5.0 2.5 5.5 9.5 2.0 10.5 ns t pzh output enable time 5.0 2.0 5.5 10.0 1.5 11.0 ns t pzl output enable time 5.0 1.5 5.5 9.5 1.5 10.5 ns t phz output disable time 5.0 2.5 6.5 11.0 1.5 12.5 ns t plz output disable time 5.0 1.5 5.0 8.5 1.0 9.5 ns symbol parameter v cc (v) (10) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units t yp. guaranteed minimum t s setup time, high or low, d n to le 5.0 1.5 3.0 3.5 ns t h hold time, high or low, d n to le 5.0 ?.5 0 0 ns t w le pulse width, high 5.0 2.0 3.5 4.0 ns symbol parameter conditions typ. units c in input capacitance v cc = open 5.0 pf c pd po w er dissipation capacitance ac act v cc = 5.0v 25.0 42.0 pf
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 9 physical dimensions dimensions are in inches (millimeters) unless otherwise noted. figure 1. 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide pa ck ag e number m20b
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 10 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 2. 20-lead small outline package (sop), eiaj type ii, 5.3mm wide pa ck ag e number m20d
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 11 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 3. 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa ck ag e number mtc20
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 12 physical dimensions (continued) dimensions are in inches (millimeters) unless otherwise noted. figure 4. 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pa ck ag e number n20a
74ac573, 74act573 octal latch with 3-state outputs ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac573, 74act573 rev. 1.5 13 tradem a rks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intend ed to be an exhaustive list of all such trademarks. acex across the board. around the world. activearray bottomless build it now coolfet crossvolt ctl current transfer logic dome e 2 cmos ecospark ensigna fact quiet series fact fast fastr fps frfet globaloptoisolator gto hisec i-lo implieddisconnect intellimax isoplanar microcoupler micropak microwire msx msxpro ocx ocxpro optologic optoplanar pacman pop power220 power247 poweredge powersaver powertrench programmable active droop qfet qs qt optoelectronics quiet series rapidconfigure rapidconnect scalarpump smart start spm stealth superfet supersot -3 supersot -6 supersot -8 syncfet tcm the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinywire trutranslation p serdes uhc unifet vcx wire disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild? worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ich, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. re v. i24

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